CSI2 Video Multiplexor
The CSI2MUX-A1-F connects to 4 CSI2 cameras, multiplexes the video streams, and sends out a multiplexed CSI2 stream, where each camera input is assigned a different Virtual Channel.
The CSI2MUX-A1-F comprises modified versions of two VLSI Plus’ IP cores, and glue logic. The two IP cores are:
・1 to 4 instantiations of VLSI SVR-CSI-4 Serial Video Receivers;
・1 instance of VLSI Plus SVT-CS4-AP2 Multiplexing Serial Video Transmitter core, modified and optimized.
For optimal usage of FPGA resources, the user is provided with compilation switches, which determine the maximum number of supported cameras (from 1 to 4), the number of data lanes for each camera (from 1 to 4), and the number of data lanes at the output (again, from 1 to 4). The actual number of cameras and lanes is programmable, and can be set to any value up to the maximum values set by the compilation switches.
- HW Mod