組み込み機器開発の効率化を図る、組み込みIPの一覧です。

組み込み用ASIC IP製品/IP一覧

各社開発しているカスタムASICに搭載可能なIPコアに利用可能、利用実績のある組み込み製品/IPリストです。

12 ページ中 1 ページ目(1~10 IP)

組合せ実績の多いIP順

ベンダー公式

DC (Display Controller) - DC series

ベリシリコン株式会社

VeriSilicon's display controller has been deployed in various product segments like wearables, high end surveillance cameras, TV processors, and automotive application processors. The flexible display interfaces, such as MIPI DBI (Type A, B, C) and SPI provides the power-efficient interface from display controller to display panel. The built-in pixel processing engine is both versatile and configurable, including scaling, blending, rotation, color conversion, dither and more. It provides system flexibility, lower bandwidth and lower power given less trips to and from DDR. The embedded decompress or module will consume directly the compressed data produced by VeriSilicon’s IPs as well as third-party IPs. This delivers even lower bandwidth and power. The DCNano display controller is driven by the wearable products, which demand for the lowest power and most compact silicon footprint. The DC8000 display controller is developed for complex SoC driving 4K2K display, which constantly operate on extreme low bandwidth condition. Each Display Controller IP is built from proven efficient pixel processing technology scalable to cover wide range of applications. <DCNano> Extreme compact in silicon area, extreme low power for wearable and MCU, scalable up-to 1080p. <DC8000> High performance, addressing 4K and 8K products, with built-in rich set of capabilities such as composition, scaling, rotation to lower the overall system bandwidth.

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ベンダー公式

DSP (Digital Signal Processor) - ZSP series

ベリシリコン株式会社

Digital Signal Processors (DSPs) are specialized processors optimized for signal processing computations and data flow. VeriSilicon’s ZSP Digital Signal Processor cores strike the perfect balance between performance, power consumption and cost for a wide range of applications including Audio, Voice and Wireless. There are multiple ZSP cores available to match the different PPA and system requirements of different applications. ZSP cores are also compatible with each other, enabling customers to easily evolve as the application demands change.

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ベンダー公式

VPU (Video Processor Unit) - Hantro series

ベリシリコン株式会社

Hantro Video IP is a family of video decoder and encoder semiconductor IP cores that has been deployed in more than one billion chips in the aggregate worldwide. Hantro Video IP is used by more than 90 semiconductor companies, including multiple tier-1 companies in different market segments such as smartphones, feature phones, digital still cameras, tablets, digital TV, set-top boxes, surveillance cameras, video cameras and automotive infortainment. Hantro Video IP provides semiconductor manufacturers a lowest risk solution for integrating high performance, low latency and ultra low power video capability into their chips.

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ベンダー公式

VIP (Vison Image Processing) - VIP series

ベリシリコン株式会社

Machine vision is becoming a critical need in many automotive, industrial, medical, security and even retail markets. VeriSilicon's Vision IP (VIP) solution is one of the first licensable vision engines to achieve OpenVX 1.0 conformance as a dedicated vision processing block. With Algorithm-Level Programmability? VIP allows for easy and rapid development of programmable applications approaching fixed function performance and efficiency. It is extremely fast and consumes less power. It is perfect for adaptable mass-market applications as well as for high-end solutions in automotive ADAS systems that require object identification, pattern recognition and similar vision related features.

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ベンダー公式

GPU (Graphics Processing Unit) - GC series

ベリシリコン株式会社

Our impressive range of scalable, licensable VeriSilicon (Vivante) GPU cores addresses the rapidly advancing expectations of the semiconductor marketplace from small form-factor IoT type MCUs with low power consumption to powerful SoCs perfect for automotive and high end multimedia applications. Vivante GPUs are designed to fit any die size and power budget and are among the most cost effective solutions available anywhere.

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■業界最先端の超低消費電力 ハイバーネート・モード動作で外部にクロックを供給可能なSensorStrobe™により、システム全体の消費電流を大幅に低減。 ■最先端のセキュリティ 速い暗号化によりお客様のアルゴリズムに読出し保護を提供 不正コードによるデバイスへの再書き込みを防止する書込み保護 ■堅牢な動作 ディープ・スリープ・モードでの完全な電圧モニタリング ECC機能を備えたフラッシュ・メモリ パリティ・エラー検出機能を備えたSRAMメモリ 割り込みを介した32 kHz LFXTALの故障検出

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Arm Cortex-A9 ソフトウェア開発実践講座

株式会社DTSインサイト

本コースは、Arm純正統合開発環境「DS-5」を使用して、Arm Cortex-A9向けの組込みプログラムを作成する際のポイントを、講義とサンプルプログラムによる実機実習を通して習得します。Arm Cortex-A9が搭載された評価ボードもプレゼントします♪ 講座内容:  ① ARM アーキテクチャイントロダクション  ② Arm コンパイラの使用方法の基礎  ③ パフォーマンス監視ユニットの使用方法  ④ Cortex-A9 マイクロプロセッサ起動プロセス  ⑤ システム起動処理演習と DS-5 の使い方(1)  ⑥ バリアについて  ⑦ ARM-v7A のキャッシュと分岐予測  ⑧ システム起動処理演習と DS-5 の使い方(2)  ⑨ メモリマネジメント  ⑩ MMU の設定演習  ⑪ 例外処理 ARM アーキテクチャ v6/v7  ⑫ 汎用割り込みコントローラプログラミング ⑬ 割り込み処理演習

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ベンダー公式

DB9200 – 2D Graphics Rendering Engine

Digital Blocks, Inc.

The DB9200 2D Graphics Rendering Engine IP Core (Verilog Cores DB9200AXI4, DB9200AXI, DB9200AHB) contains all the features of the DB9100, adding Geometry Drawing features

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ベンダー公式

DB9100 – BitBLT 2D Graphics Engine

Digital Blocks, Inc.

The DB9100 BitBLT 2D Graphics Engine IP Core (Verilog Cores DB9100AXI4, DB9100AXI, DB9100AHB, DB9100AVLN) reads graphics command sets originated by the host processor and processes up to full-screen size blocks of pixels from up to 3 simultaneous streaming sources while performing one of 256 bitwise operations on the streaming sources. The DB9100 BitBLT can perform graphics operations as simple as fill all screen memory with a solid color to drawing a solid-fill rectangle with horizontal and vertical boundary lines.

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The Digital Blocks DB9000AXI TFT LCD/OLED Display Processor & Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a TFT LCD/OLED panel. The DB9000AXI contains a selectable 256 / 128 / 64 / 32-bit AXI Master Interface that targets 8K/4K higher resolution, higher color depth TFT LCD/OLED panels, with their resulting high frame buffer memory data bandwidth requirements, down to 320x240 VGA resolutions.

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