NOESIS TECHNOLOGIES の製品・IP一覧

ベンダー公式

ntRSE - Reed Solomon Encoder

2016/10/21

The ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the encoder ideal for fully adaptive FEC applications. The ntRSE core supports continuous or burst encoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.

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ベンダー公式

ntTPCD - Turbo Product Decoder

2016/10/21

The ntTPCD decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The decoded soft information is output in the same or-der. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. These words are called test patterns and their num-ber is pre-configurable. All C1, C2, C3 words decoding takes place in a main decoding unit, the programmable ele-mentary Soft Input Soft Output (SISO) decoder. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs. The architecture of one elementary SISO decoder is parameterizable in terms of maximum constituent code size (64,128,256 bits), optional 3D codes support and maximum parallel test patterns processing (8,16,32) and soft bits.

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ntVIT - Viterbi Decoder

2016/10/21

Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to correct errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB increase in coding gain over hard-decision decoding. Data can be received continuously or with gaps.

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ベンダー公式

ntTPCE - Turbo Product Encoder

2016/10/21

The ntTPCE core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The row encoder encodes the data row-wise (C2). The encoded data produced from the row encoder are stored in an intermediate memory and reordered in a column-wise fashion. Once a full column has been written in the memory, the data are encoded column-wise by the col-umn encoder (C1). When 3d encoding is employed, the encoded data produced from the column encoder are stored in an intermediate memory and reordered in a 3d-plane-wise fashion. The C3 data planes are encoded by an SPC(4,3) encoder (C3). Before output encoded information data are being reordered in row-wise fashion.

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ntRSD - Reed Solomon Decoder

2016/10/21

The ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal
for fully adaptive FEC applications. The ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications. The ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. The ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.

  • MW
  • Drv
  • OS
  • FPGA
  • ASIC
  • HW M
  • 評ボ
  • 評環
  • 開環
用途:
通信(有線)
通信(無線)

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