The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance. This system contains an 8 master, 16 slave AXI4 multi-matrix for supporting multiple high speed user AXI masters while providing high performance with Cortex-A5 class processors.
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional performance. This AHB Multi-matrix system contains a flexible Power Management Unit for controlling power sequencing of the CPU and peripherals. The PMU can easily be extended to control additional cores, peripherals and even analog subsystems on the same SOC.
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem contains a flexible Power Management Unit that controls the power sequence of the CPU as well as the APB peripherals. The PMU can easily be extended to control additional cores, peripherals and even mixed signal subsystems on the same SOC.
The I3C Sensor Subsystem is an AMBA® based system that is useful in building low power SOCs needing sensor interfaces through I3C. The subsystem includes the I3C Dual Role Master controller which meets the MIPI I3C standard
The I3C Dual-Role Master controller is a highly configurable I3C master that can be used in microcontroller based environments to provide I3C connectivity to any device. It contains master capabilities as well as the same features as the I3C Advanced Slave. It can be configured in a number of different ways to allow the core to use the minimum amount of logic to reduce both area (cost) and power.