innosilicon technology ltd. の製品・IP一覧

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DDR/LPDDR 4/3/2 combo PHY&Controller, up to 2800Mbps

2017/01/05

A performance leading DDR PHY that supports DDR4/LPDDR4/DDR3/LPDDR3/DDR2/LPDDR2/DDR at speeds up to 2800Mb/s and in any bus width. Silicon proven in volume manufacturing, and test chips, the PHY combines low power consumption with its small size. This compact form factor translates into low I/O pin count, simplifying both package substrate and PCB. Potentially allowing for board level routing using only 2 layers. Leveraging a choice of DFI V2.0/V2.1/V3.0/V3.1 standards, the PHY can be integrated with our companion memory controller or major compatible 3rd party options. It is fully register controlled via an APB and production testing is simplified through at-speed BIST, loopback modes, and boundary scan. A self-contained, but modular design, the PHY contains the I/Os, ESD, a timing synch module DLLs and can be expanded to a virtually unlimited bus width. Optional components include: customer specific bus widths, integrated PLLs, custom pinouts, and the Innosilicon memory controller which supports AHB/AXI and FIFO interfaces. We can create the custom DDR solution that meets your needs while handling whatever level of integration support you require.
- For more info: http://www.innosilicon.com/html/ip-solution/1.html

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通信(有線)
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ストレージ
画像処理
音声処理
演算処理

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USB2.0/3.0/HISC PHY (Device/Host/OTG/Hub)

2017/01/05

The INNOSILICON USB 2.0/3.0/HSIC PHY (Host/Device/Hub/OTG) is fully compliant with UTMI+ level 3 Rev 1.0 specification. Offering excellent performance combined with a die size up to 30% less than the competition, this PHY is the perfect companion to your design. The impressively small die size offers all functionality needed for a complete USB solution. HS, FS and LS support with OTG along with all required I/Os, primary and secondary ESD, self-calibrated DP/DM termination and an integrated PLL. The UTMI+ interface can be pre-configured for either a 30MHz 16-bit, or 60Mhz 8-bit data interface. If your solution requires more than one USB port, a further size efficiency can be had by choosing a multi-port solution. The INNOSILICON USB 2.0 PHY is available in 1, 2, 3 and 4-port configurations. To support production test with high coverage, this PHY includes BIST, loop back, and boundary scan functionality.
– for more info: USB2.0: http://www.innosilicon.com/html/ip-solution/2.html
USB3.0: http://www.innosilicon.com/html/ip-solution/13.html

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用途:
通信(有線)
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ストレージ
画像処理
音声処理
演算処理

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Multi-SERDES PHY SATA3/PCIe3/XAUI

2017/01/05

The Innosilicon Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2 and XAUI with full compliance. High data rates are accurately achieved through fully programmable TX drivers and auto-calibrated on-die terminations. The design is completely self-contained including: I/O pads, primary and secondary ESD for simple integration and production testing is simplified through at-speed BIST, loopback and boundary scan. As with all Innosilicon IP, we are ready to provide the custom solution that meets your needs.
- for more info: http://www.innosilicon.com/html/ip-solution/6.html

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  • FPGA
  • ASIC
  • HW M
  • 評ボ
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用途:
通信(有線)
通信(無線)
ストレージ
画像処理
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演算処理

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eDP/DP PHY

2017/01/05

The Innosilicon eDP DP PHY is a highly reliable solution for your display interface requirements. It is fully compliant with DP 1.0 and eDP 1.3 standards, and capable of driving 2.7Gb/s per lane in configurations up to 4 lanes. Designed with ease of integration in mind, it is configurable via its I2C, APB or CPU interface, and production testing is simplified through at-speed BIST, scan, loopback modes and boundary scan. The PHY itself is fully self-contained, requiring no end user synthesis, and is optimized for both area and power. It contains all the necessary PHY components such as I/Os, primary and secondary ESD, PLL and the data symbol Synchronization/Serialization unit. As with all Innosilicon IP, we are ready to provide the custom solution that meets your needs.
- for more info: http://www.innosilicon.com/html/ip-solution/7.html

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用途:
通信(有線)
通信(無線)
ストレージ
画像処理
音声処理
演算処理

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HDMI 1.4/2.0 Tx PHY & Controller

2017/01/05

The Innosilicon low power, mixed signal HDMI-IPTM Transmitter provides a complete HDMI 2.0/1.4 standard compliant interface solution for delivering video and audio streams. With a transmit rate up to 6 Gb/s per link, it supports 3D and resolutions ranging from 480i to 4Kx2K@60/50Hz for UHD displays. Optimized for both area and power, this HDMI solution contains all necessary PHY components including I/Os, primary and secondary ESD, and PLL along with video, audio and control processing units. This PHY is designed with production test support in mind with BIST, loop back and boundary scan all incorporated.
- for more info: http://www.innosilicon.com/html/ip-solution/3.html

  • MW
  • Drv
  • OS
  • FPGA
  • ASIC
  • HW M
  • 評ボ
  • 評環
  • 開環
用途:
通信(有線)
通信(無線)
ストレージ
画像処理
音声処理
演算処理